1. Field of the Invention
The present invention relates to testing the design of a prescribed system using field programmable gate arrays prior to implementation on mass-produced application-specific integrated circuits (ASICs).
2. Background Art
Local area networks use a network cable or other media to link stations on the network. Each local area network architecture uses a media access control (MAC) enabling network interface devices at each network node to access the network medium.
Switched local area networks such as Ethernet (IEEE 802.3) based systems are encountering increasing demands for higher speed connectivity, more flexible switching performance, and the ability to accommodate more complex network architectures. Hence, network switch designers and test engineers need to be able to minimize the time and expense needed to evaluate designs during prototyping of Ethernet-based network systems, for example an integrated multiport switch as illustrated in commonly-assigned U.S. Pat. No. 5,953,335.
Integrated network switches are implemented by reduction to silicon as an application-specific integrated circuit. Implementation of such integrated network switches using application-specific integrated circuits (ASICs) typically requires reduction to silicon of large amounts of programming code, written for example at Register Transfer Level (RTL) using Hardware Description Language (HDL). The programming code is used to specify the operations for the network switch.
Typically field programmable ASICs, for example field programmable gate arrays (FPGAs), can be used for testing the design, logic and operation of a device under test on a test board; once the design of the device under test has been fully tested and validated, the design of the device under test is converted to a mask programmable ASIC for production purposes.
A problem with testing more complex designs involves the limited availability of large scale FPGAs for testing the more complex designs. In particular, the more complex designs (e.g., a high-speed network switch) often exceeds the capacity of field programmable gate arrays (e.g., 150 k usable gates). Moreover, attempts to partition the design onto separate FPGAs interconnected on a test board are not possible, since the original design uses shared resources to optimize space on the silicon chip. Hence, the testing of more complex designs requires that the design be simulated in software, or that a limited number of test ASIC samples be manufactured using mask programming to test the more complex design. Consequently, testing becomes more difficult as design changes need to be made.
There is a need for an arrangement that enables a design to be partitioned into multiple field programmable gate arrays for testing of the design prior to commercial production.
There also is a need for an arrangement that enables design revisions to be implemented using existing test procedures, with minimal modification to the test equipment.
These and other needs are attained by the present invention, where a test system for a design of a network device under test, having multiple design modules, includes multiple field programmable gate arrays configured for performing operations of the respective design modules. The test system also includes shared resources, where each field programmable gate array includes resource control logic for accessing the shared resources according to a prescribed shared resource protocol. Hence, the resource control logic of each of the field programmable gate arrays cooperate to ensure there is no interference between the multiple field programmable gate arrays for the shared resources. Hence, a design can be partitioned into multiple field programmable gate arrays, enabling testing of large scale designs; moreover, the partitioning of the design into multiple FPGAs enables each design module to be separately controlled, enabling design revisions to different design modules as necessary, without any other modification to the remaining test system.
One aspect of the present invention provides a method of testing a design for an integrated device having multiple design modules. The method includes dividing the design modules into respective field programmable gate arrays based on prescribed module boundaries, identifying shared resources used by the multiple design modules, and adding resource control logic to each field programmable gate array for accessing the shared resources according to a prescribed shared resource protocol.
Another aspect of the present invention provides a test system for testing a design for an integrated device having multiple design modules. The test system includes a plurality of field programmable gate arrays, each configured for performing prescribed operations for the corresponding one of the design modules. Each field programmable gate array also includes a resource control logic unit. The test system also includes a shared resource configured for use by the field programmable gate arrays according to a prescribed shared resource protocol, each of the resource control logic units controlling access by the corresponding field programmable gate array to the shared resources according to the prescribed shared resource protocol.
Additional advantages and novel features of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the present invention may be realized and attained by means of instrumentalities and combinations particularly pointed in the appended claims.